Wafer bonding for monolithic integration of Si CMOS VLSI electronics with III-V optoelectronic devices

Abstract

GaAs-on-silicon epitaxy techniques as well as wafer bonding GaAs to Si, have been developed to overcome lattice mismatch in order to integrate optoelectronic and Si devices. However, the thermal expansion differences between these materials continues to be a limitation in using either of these approaches. After recognizing that Si devices, such as MOSFETs, are intrinsically thin and relatively strain tolerant, while optoelectronic devices, such as LEDs and lasers, are thick and very strain sensitive, this research was based on developing a better approach which involved bonding thin Si layers to thick GaAs substrates with various dielectric layers as the interface, to produce silicon-on-gallium arsenide (SonG) wafers. Such wafers are suitable for the fabrication of Si SOICMOS electronics and the subsequent monolithic integration of high performance optoelectronic devices. Future goals for this work include bonding fully processed SOI-CMOS wafers to the GaAs, rather than silicon wafers containing no electronics. With the successful development of SonG techniques for monolithic integration, it will be possible to use full-wafer and batch processing techniques for the production of sophisticated economically viable optoelectronic integrated circuits.