An exploratory design of a 65 nm CMOS buck converter for maximum efficiency
Author(s)Lin, Doris, M. Eng. Massachusetts Institute of Technology
Designing a 65nm buck converter for maximum efficiency
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
David J. Perreault.
MetadataShow full item record
Portable battery-operated consumer devices, such as mp3 players, cell phones, and digital cameras, are becoming ever more prevalent and so the need for long battery life is increasingly important. These small devices contain power converters that produce lower supply voltages from the fixed battery voltage source. For long battery life, it is necessary to maximize the efficiency of the power converter. A design is proposed for the topology and control of a 65 nm CMOS DC/DC switch-mode converter converting a 3 V battery supply to a 1.2 V output voltage for a maximum output current of 100 mA. The goal of the project was to maximize converter efficiency and improve on the maximum 40% efficiency of a traditional linear regulator. With the proposed topology and control scheme described in this report, the buck converter operates at a switching frequency of 10 to 75 MHz with a maximum efficiency of 93.63%.
Includes bibliographical references (p. 75-76).Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
DepartmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.; Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.