Low-power amplifier chopper stabilization for a digital-to-analog converter

Abstract

Modern portable media devices demand low-power and low-noise performance from the internal digital-to-analog converter. CMOS design has allowed for oversampling sigma-delta modulation to achieve these goals. However, noise is typically limited by the kT/C noise in the switched capacitor filter following the digital modulation. These filters also require a large amount of on-chip capacitance. The goal of this project is to design a continuous-time output stage for a DAC. A continuous-time output requires much less capacitance than the SC filter. Chopper stabilization is applied to the amplifier to reduce the low-frequency noise. The challenge of this architecture is maintaining amplifier harmonic performance and transient performance. In simulations, chopper stabilization improved signal-to-noise ratio by 11dB while maintaining system level harmonic distortion performance.