An instruction scheduling algorithm for communication-constrained microprocessors

Abstract

This thesis describes a new randomized instruction scheduling algorithm designed for communication-constrained VLIW-style machines. The algorithm was implemented in a retargetable compiler system for testing on a variety a different machine configurations. The algorithm performed acceptably well for machines with full communication, but did not perform up to expectations in the communication-constrained case. Parameter studies were conducted to ascertain the reason for inconsistent results.