A low power high power supply rejection ratio bandgap reference for portable applications
Name
405613481-MIT.pdf
Description
Full printable version
Size
28.14 MB
Format
Adobe PDF
Checksum (MD5)
106ad31dda7436a19fd45747316b5134
Author(s)
Sundar, Siddharth
Advisor(s)
Eric Kimball and Michael Perrott.
Date Issued
2008
Publisher
Massachusetts Institute of Technology
Abstract
A multistage bandgap circuit with very high power supply rejection ratio was designed and simulated. The key features of this bandgap include multiple power modes, low power consumption and a novel resistor trimming strategy. This design was completed in deep submicron CMOS technology, and is especially suited for portable applications. The bandgap designed achieves over 90 dB of power supply rejection and less than 17 microvolts of noise without any external filtering. With an external filtering capacitor, this performance is significantly enhanced. In addition, the design includes an efficient voltage-to-current converter and a fast-charge circuit for charging the external capacitor.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.
Includes bibliographical references (p. 86-87).
Subjects
Electrical Engineering and Computer Science.
MIT Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Terms of Use
M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission.
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission.
Persistent DSpace Link
