| dc.contributor.advisor | Thomas F. Knight, Jr. | en_US |
| dc.contributor.author | Ruan, Helen H. (Helen Hui), 1974- | en_US |
| dc.date.accessioned | 2009-10-01T15:20:57Z | |
| dc.date.available | 2009-10-01T15:20:57Z | |
| dc.date.issued | 1998 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.1/47546 | |
| dc.description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998. | en_US |
| dc.description | "January 1998." | en_US |
| dc.description | Includes bibliographical references (leaf 43). | en_US |
| dc.description.statementofresponsibility | by Helen H. Ruan. | en_US |
| dc.format.extent | 43 leaves | en_US |
| dc.language.iso | eng | en_US |
| dc.publisher | Massachusetts Institute of Technology | en_US |
| dc.rights | M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission. | en_US |
| dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | en_US |
| dc.subject | Electrical Engineering and Computer Science | en_US |
| dc.title | Analysis and design considerations for high performance caches | en_US |
| dc.type | Thesis | en_US |
| dc.description.degree | B.S. | en_US |
| dc.description.degree | M.Eng. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
| dc.identifier.oclc | 40495503 | en_US |
