Micro-architectural analysis of SPACERAM processing element

Abstract

SPACERAM is a SIMD architecture optimized for symbolic spatial computations implemented with multiple banks of DRAM combined with an array of processing elements. Such an architecture facilitates very high processor-memory bandwidth and hence allows for applications requiring orders of magnitude higher processing and update rates per DRAM than any current hardware. The array of processing elements process data coming simultaneously from several memory blocks by applying appropriate shifting and lookup table updates to them. Every processing element contains a permuter which makes it possible to assign data bits from any DRAM block to any functional block within the processing element as specified by controller setup. The lookup table is implemented as a common bus shared by all the processing elements. Micro-architectural analysis of such a processing element presents various possible implementations and trade-off issues associated with them.