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A 4th order continuous-time [Delta] [Epsilon] ADC with VCO-based integrator and quantizer

Author(s)
Park, Matthew Jeremiah
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Alternative title
Fourth order continuous-time [Delta] [Epsilon] ADC with VCO-based integrator and quantize
Other Contributors
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Michael H. Perrott.
Terms of use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582
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Abstract
The use of a VCO-based integrator and quantizer within a continuous-time (CT) [Delta] [Epsilon] analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 [mu]m CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADC's, which exclusively made use of the output frequency. Furthermore, the proposed architecture includes a scheme for performing fast dynamic element matching (DEM), enabling first-order shaping of unit-element mismatch in all feedback DAC's.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.
 
In title on title page, "[Delta]" and "[Epsilon]" appear as upper-case Greek letters.
 
Includes bibliographical references (p. 135-140).
 
Date issued
2009
URI
http://hdl.handle.net/1721.1/47755
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

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