Effective modeling of throughput time in semiconductor assembly processes
Author(s)
Cervantes José A. (José Armando), 1973-
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Advisor
Kevin Otto and Stanley B. Gershwin.
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We develop discrete event simulation (DES) models of a semiconductor assembly process capable of predicting average throughput time (TPT) within 6% of factory-floor measured average TPT. This represents a significant improvement over current DES models in the semiconductor industry, which commonly yield average TPTs that are 25% to 50% less than those measured on the factory floor. We accomplish this improvement by (1) constructing a separate area model of the system's constraint, (2) inputting an exact lot-starts schedule to the model, and (3) using failure parameters which are operation dependent rather than time dependent. In addition, we devise heuristics to parallelize the simulation process and significantly reduce computational expense in DES models, thereby affording the inclusion of detailed factors. We perform various sensitivity studies on the assembly's constraining process which indicate that operators and shift effects do not have a significant effect on average TPT. We also apply the series-parallel flow-line analytical model developed by Gershwin [8] and Burman [2], obtaining average TPTs which are 27% of factory-floor measured average TPT with numerical computational times of under a second.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering; and, (S.M.)--Massachusetts Institute of Technology, Sloan School of Management, 1998. Includes bibliographical references (p. 155-156).
Date issued
1998Department
Massachusetts Institute of Technology. Department of Mechanical Engineering; Sloan School of ManagementPublisher
Massachusetts Institute of Technology
Keywords
Mechanical Engineering, Sloan School of Management