Device design and process technology for sub-100 nm SOI MOSFET's

Abstract

Silicon-on-insulator (SOI) MOSFET's are an attractive alternative to bulk-silicon MOSFET's in the sub-100 nm gate length regime due to improved performance and/or scalability. The SOI layer thickness in SOI MOSFET's can be sized so that the channel is either partially- or fully-depleted-of majority carriers. Partially-depleted (PD) SOI MOSFET's are easier to manufacture than fully-depleted (FD) SOI MOSFET's because a thicker SOI film can be used. However, PDSOI MOSFET's are difficult to design due to floating-body effects. FD-SOI MOSFET's are easier to design and are more scalable than PD-SOI MOSFET's. However, in the sub- 100 nm gate length regime, fully-depleted SOI MOSFET's are difficult to manufacture because a bottom gate is required for electrostatic integrity. In this thesis, floating-body effects in PD-SOI MOSFET's and process technology for fabrication of double-gate FD-SOI MOSFET's will be investigated. Floating-body effects in PD-SOI MOSFET's result from floating-body voltage modulation by AC and DC changes in source, drain, gate, and substrate terminal voltages. This modulation of the floating-body voltage results in modulation of the drain current. AC modulation of the floating-body voltage occurs through capacitive coupling to rapidly switching terminal voltages. DC modulation of the floating-body voltage occurs through diode currents and impact ionization. Because the time constants of these processes are very different, the DC and AC I-V behavior of floating-body PD-SOI MOSFET's are very different from each other, as well as very different from body-contacted SOI MOSFET's or bulk MOSFET's with the body tied to a fixed voltage. Floating-body effects on I-V behavior, how they are important in CMOS digital operation, and how they are affected by device design are described and modeled. Another consequence of floating-body behavior is history dependence in I-V behavior. Rapid switching of terminal voltages induce nearly-negligible changes in body majority carrier content since body majority carriers are trapped by body-source/drain junction diodes. However, the change in body majority carrier content can become significant over many switching cycles, eventually reaching a "switching-steady-state" value if kept switching (different value for different switching patterns), and can return to the initial value if the terminal voltages are returned to the initial settings and enough time is allowed to reach equilibrium. This "hysteretic" variation of the body majority hole content is problematic because device I-V behavior changes with changing body majority carrier content. Device design to minimize hysteretic behavior will be presented. Once the hysteretic I-V behavior of floating-body PD-SOI MOSFET's has been understood, floating-body PD-SOI CMOS technology can be optimized to maximize drive current while minimizing hysteresis. This optimized PD-SOI technology can then be compared to bulk CMOS technology. This was done using the 2-D numerical simulator MEDICI in a optimization framework based on the International Technology Roadmap for Semiconductors for the 100 nm-, 70 nm-, and 50 nm-technology nodes. And finally, double-gate fully-depleted SOI MOSFET's technology was explored. A method to fabricate bury a bottom-gate under a FD-SOI MOSFET was developed based on a flip-bond- transfer technique. This technique is based on chemical-mechanical-polish and wafer fusion bonding. Double-gate SOI MOSFET's were fabricated based with this technique, and a self-alignment scheme for alignment of the bottom-gate which to the top-gate was explored.