Reliability of GaN high electron mobility transistors on silicon substrates

Abstract

GaN High Electron Mobility Transistors are promising devices for high power and high frequency applications such as cellular base stations, radar and wireless network systems, due to the high bandgap and high breakdown field of GaN. However, their reliability is the main hindrance to the deployment of these transistors in a wide scale. In this study, we have investigated the reliability of GaN HEMTs grown on Si substrates. The large lattice and thermal mismatch between GaN and Si adds an additional reliability concern as compared to conventional substrates such as SiC and sapphire. We have performed systematic electrical stress experiments to understand the physics of degradation in these devices. Relevant device parameters are recorded continuously during these stress tests by a benign characterization suite. We conclude from these experiments that high voltage stress conditions are more effective in degrading the device than high current conditions. High voltage stress is found to impact the device in two different ways. The first is increased trapping in the large number of traps in the highly mismatched device structure even before any stress. The second is through the converse piezoelectric effect discussed by Joh et al. for GaN-on-SiC devices. We also have found evidence that these two mechanisms are connected. We have used UV illumination to enhance detrapping and shown that trapped electrons screen the electric field in the device and increase the critical voltage at which gate current degrades.