Show simple item record

dc.contributor.advisorAnantha P. Chandrakasan.en_US
dc.contributor.authorYip, Marcusen_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2010-03-25T15:31:27Z
dc.date.available2010-03-25T15:31:27Z
dc.date.copyright2009en_US
dc.date.issued2009en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/53324
dc.descriptionThesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.en_US
dc.descriptionCataloged from PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (p. 109-112).en_US
dc.description.abstractMicropower sensor networks have a broad range of applications which include military surveillance, environmental monitoring, chemical detection and more recently, medical monitoring systems. Each node of the sensor network requires energy efficient circuits powered off small batteries or harvested energy. In such systems, a single reconfigurable analog-to-digital converter (ADC) is needed to digitize a wide range of signals with varying bandwidth and resolution requirements. This thesis describes the design of an ADC whose power scales exponentially with resolution and linearly with frequency to maximize the system lifetime. The proposed ADC has reconfigurable resolution from 5 to 10-bits and a scalable sample rate from 0 to 1-MS/s. The successive approximation register (SAR) architecture was chosen for its highly digital nature which enables low voltage operation. The supply voltage can be scaled from 1V down to 0.4V such that the ADC maintains a constant energy efficiency across all modes of operation when normalized with respect to sample rate and resolution. A capacitive digital-to -analog converter (DAC) in a split capacitor topology with a sub-DAC is used to minimize the DAC power and area. Top plate switches are used to decouple the MSB capacitors as resolution is scaled to avoid parasitic loading of the DAC. The DAC capacitors are laid out in a common-centroid configuration with edge effects minimized at each resolution mode to improve matching. A fully dynamic latched comparator is used to avoid static bias currents.en_US
dc.description.abstract(cont.) Power gating of the digital logic is used to reduce leakage power at low sample rates. Reconfigurability between single-ended or differential modes enables a power versus performance trade-off. Lastly, programmable sampling duration and internal bootstrapping is used to maintain sampling linearity at low voltages. The ADC has been submitted for fabrication in a low power 65nm digital CMOS process and simulation results are presented.en_US
dc.description.statementofresponsibilityby Marcus Yip.en_US
dc.format.extent112 p.en_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleA highly digital, reconfigurable and voltage scalable SAR ADCen_US
dc.typeThesisen_US
dc.description.degreeS.M.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.identifier.oclc550606294en_US


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record