dc.contributor.author | Agarwal, Anant | |
dc.date.accessioned | 2010-04-27T16:32:15Z | |
dc.date.available | 2010-04-27T16:32:15Z | |
dc.date.issued | 2009-09 | |
dc.identifier.isbn | 978-0-7695-3847-1 | |
dc.identifier.issn | 1550-4794 | |
dc.identifier.other | INSPEC Accession Number: 10869154 | |
dc.identifier.uri | http://hdl.handle.net/1721.1/54237 | |
dc.description.abstract | The multicore revolution has changed the way we think about computing. The same movement has also changed the way we look at on-chip interconnect because it is a key determinant of the performance and power efficiency of multicores. This talk will highlight some of the lesser known issues and opportunities of on-chip interconnect, such as protection, programming ease, and the impact on the basic structure of our software. The talk will borrow heavily from our experiences with on-chip interconnect in university research with the 16-core Raw multicore processor, in a commercial environment with Tilera's 64-core Tile processor, and in a future 1K-core multicore processor called ATAC that integrates optical and electrical interconnects. | en |
dc.language.iso | en_US | |
dc.publisher | Institute of Electrical and Electronics Engineers | en |
dc.relation.isversionof | http://dx.doi.org/10.1109/HOTI.2009.28 | en |
dc.rights | Article is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use. | en |
dc.source | IEEE | en |
dc.title | The Other Face of On-Chip Interconnect | en |
dc.type | Article | en |
dc.identifier.citation | Agarwal, A. "Keynote: The Other Face of On-Chip Interconnect," in Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009. HOTI 2009. pp.xii-xii, 25-27 Aug. 2009. ©2009 Institute of Electrical and Electronics Engineers. | en |
dc.contributor.department | Massachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratory | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | en_US |
dc.contributor.approver | Agarwal, Anant | |
dc.contributor.mitauthor | Agarwal, Anant | |
dc.relation.journal | Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009. HOTI 2009. | en |
dc.eprint.version | Final published version | en |
dc.type.uri | http://purl.org/eprint/type/ConferencePaper | en |
eprint.status | http://purl.org/eprint/status/PeerReviewed | en |
dspace.orderedauthors | Agarwal, Anant | |
dc.identifier.orcid | https://orcid.org/0000-0002-7015-4262 | |
mit.license | PUBLISHER_POLICY | en |
mit.metadata.status | Complete | |