Show simple item record

dc.contributor.authorAgarwal, Anant
dc.date.accessioned2010-04-27T16:32:15Z
dc.date.available2010-04-27T16:32:15Z
dc.date.issued2009-09
dc.identifier.isbn978-0-7695-3847-1
dc.identifier.issn1550-4794
dc.identifier.otherINSPEC Accession Number: 10869154
dc.identifier.urihttp://hdl.handle.net/1721.1/54237
dc.description.abstractThe multicore revolution has changed the way we think about computing. The same movement has also changed the way we look at on-chip interconnect because it is a key determinant of the performance and power efficiency of multicores. This talk will highlight some of the lesser known issues and opportunities of on-chip interconnect, such as protection, programming ease, and the impact on the basic structure of our software. The talk will borrow heavily from our experiences with on-chip interconnect in university research with the 16-core Raw multicore processor, in a commercial environment with Tilera's 64-core Tile processor, and in a future 1K-core multicore processor called ATAC that integrates optical and electrical interconnects.en
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineersen
dc.relation.isversionofhttp://dx.doi.org/10.1109/HOTI.2009.28en
dc.rightsArticle is made available in accordance with the publisher's policy and may be subject to US copyright law. Please refer to the publisher's site for terms of use.en
dc.sourceIEEEen
dc.titleThe Other Face of On-Chip Interconnecten
dc.typeArticleen
dc.identifier.citationAgarwal, A. "Keynote: The Other Face of On-Chip Interconnect," in Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009. HOTI 2009. pp.xii-xii, 25-27 Aug. 2009. ©2009 Institute of Electrical and Electronics Engineers.en
dc.contributor.departmentMassachusetts Institute of Technology. Computer Science and Artificial Intelligence Laboratoryen_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverAgarwal, Anant
dc.contributor.mitauthorAgarwal, Anant
dc.relation.journalProceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009. HOTI 2009.en
dc.eprint.versionFinal published versionen
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen
eprint.statushttp://purl.org/eprint/status/PeerRevieweden
dspace.orderedauthorsAgarwal, Anant
dc.identifier.orcidhttps://orcid.org/0000-0002-7015-4262
mit.licensePUBLISHER_POLICYen
mit.metadata.statusComplete


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record