Energy efficient links and routers for multi-processor computer systems

Abstract

As multi-processor computer systems become more prevalent in today's computer industry, it is clear that routers and interconnection networks are critical components of these multi-processor systems. Therefore, there is a need to obtain accurate area and power models for these critical components so that we can better understand the area and power tradeoffs as we balance the on-chip and off-chip communication energy given a fixed energy budget. In this thesis, we propose an alternative method to understanding the power and area tradeoffs for routers by not solely relying on analytical models, on which most current studies done on this topic are based. Instead, in this thesis we propose analyzing the area versus power tradeoff for these routers and interconnection networks using an Application Specific Integrated Circuit (ASIC) flow in a commercially available IBM 90nm process technology. This thesis shows that multiplexer routers are more area and power efficient compared to matrix routers since matrix routers quickly exhibit a quadratic-like increase in area and power as the number of ports and port width increases. In addition, we show that there is a real gain in area when the router is shared among 4 or more cores. The savings by sharing the same router among multiple cores does not continue indefinitely, since after a certain port number and port width size, the increase in the crossbar size can no longer be compensated by sharing the router. So for a fixed port-width, there is always a sweet spot for the number of ports where a local minimum can be found for the Router Area Overheard per Core.

(cont.) By examining and analyzing the router design space, we show that for maximum area and power efficiency, it is much better to use a multiplexer router with 8-ports as opposed to matrix routers. Moreover, keeping the flit size to 32-bits or 64-bits results in a larger Router Area Overheard per Core savings as opposed to using a flit size of 128-bits. Even in situations where the core manipulates 128-bits of data, using two 64- bit routers running in parallel at the core frequency will result a larger area and power savings. Most importantly, we show that by looking at the costs and benefits of aggregation, we see that aggregation is only useful for narrow channel routers. This is because successful aggregation is a function of the crossbar complexity versus the bit/port width. By switching from a NoC with 5-port routers to higher radix routers while keeping the network bisection bandwidth approximately constant, the savings in the Router Area Overheard per Core can be up to 63%. The results of this work will allow us to calibrate our existing Orion 1.0 analytical models. We show that the source of the largest discrepancy between the synthesized results and the analytical models is the buffer and not the crossbar as we expected. The crossbar can be further optimized by designing and physically laying it out manually. The buffers were obtained using the Artisan SRAM Register File Memory Generator software, and hence they are expected to be fully optimized for power and area efficiency.

(cont.) Therefore, it appears that our analytical models for the buffer might not be accurate. In addition, the results of this study will be used to narrow down the microarchitecture of a router to be used in the Integrated Photonics Network project at the Integrated Systems Group (ISG) at the Research Laboratory for Electronics.