Quantum capacitance in scaled down III-V FETs

Abstract

As Si CMOS approaches the end of the roadmap, finding a new transistor technology that allows the extension of Moore's law has become a technical problem of great significance. Among the various candidates, III-V-based MOSFETs represent a very promising technology. In particular, low-effective mass materials with high electron velocities, such as InGaAs and InAs are of great interest. A concern with this approach is the relatively small inversion-layer capacitance that is associated with a low-effective mass channel and the limits that this imposes on the gate capacitance that can be attained from barrier thickness scaling. This can seriously limit the current driving ability of scaled down devices. In order to understand the scaling potential of III-V MOSFETs, we have built a physical gate capacitance model for III-V FETs that incorporates quantum capacitance and centroid capacitance in the channel. We verified its validity with simulations (Nextnano) and experimental measurements on High Electron Mobility Transistors (HEMTs) with InAs and InGaAs channels down to 30 nm in gate length. Our model confirms that in the operational range of these devices, the quantum capacitance significantly lowers the overall gate capacitance. In addition, our experiments suggest a large increase of the in-plane effective mass in very thin channel designs as a result of non-parabolicity, quantum confinement and biaxial compressive strain. This should help to achieve a relatively high electron concentration in future 10 nm high-k dielectric Ill-V MOSFETs. Our study provides a number of suggestions for capacitance scaling in future Ill-V MOSFETs.