Structure/processing relationships in vapor-liquid-solid nanowire epitaxy

Abstract

The synthesis of Si and III-V nanowires using the vapor-liquid-solid (VLS) growth mechanism and low-cost Si substrates was investigated. The VLS mechanism allows fabrication of heterostructures which are not readily attainable using traditional thin-film metalorganic chemical vapor deposition (MOCVD). In addition to these heterostructures, the VLS mechanism allows exploration of Si substrates as platforms for advanced III-V devices, a long-standing goal of the III-V research community, because of the potential for significant cost reductions. The approach to nanowire development first began by focusing on the binary Au/Si system. This system allowed us to understand critical parameters of our process including e-beam evaporation of Au thin-films, deposition of Au-colloid particles, pregrowth cleaning procedures and CVD growth conditions and times. Once controllable and repeatable Si nanowire epitaxy on Si substrates was established, we were able to focus on development of both III-V wires on Si substrates as well as Si substrates with topographic features and silicon-on-insulator (SOI) wafers. Growth abnormalities between Au-colloid nanoparticle catalysts and Au thin-film catalysts revealed a correlation between Au coverage on the substrate surface and Si nanowire growth rate. We found an increasing growth rate with increasing concentrations of Au catalyst particles on the wafer surface. Systematic experiments relating the nanowire growth rate to the proximity of nearest-neighbor Au-particles and Au-reservoirs were carried out and the results were found to be in good agreement with a SiH4 reaction model which associates decomposition to form SiH2 with higher nanowire growth rates. III-V nanowire growth on Si substrates was investigated as a possible route to the realization of high performance compound semiconductor devices on low cost substrates. For this study, GaP and InP were chosen as starting points for III-V nanowire integration with Si. Initial studies which focused on III-V wire epitaxy found that when Au-catalyst particles were treated with the group-III precursors before growth, there was an increase in the fraction of catalyst particles yielding wire growth and in the number of wires growing vertically from the substrate. Axial nanowire heterostructures of GaP(w)/InP(w)/GaP(w) were fabricated using MOCVD on Si (111) substrates. Growth temperature was found to be critical in the formation of GaP/InP axial heterostructures with minimal simultaneous lateral 3 overgrowth of InP. Analysis of the second GaP segment on InP suggests that an increase in growth temperature while Au is in direct contact with InP results in the InP dissolving into the Au particle and disappearance of the heterostructure. Si substrates were used as a foundation to explore more complex silicon structures, such as ordered arrays and SOI architectures. Although several routes initially looked promising for ordered array development, inverted pyramid arrays on Si (100) substrates were found to be the most successful. Silicon-on-insulator substrates were also explored for VLS nanowire growth and both Si nanowire field effect transistors and GaP nanowire cantilevers were successfully demonstrated on this platform.