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Membrane technology for the fabrication of three-dimensional photonic crystals

Author(s)
Patel, Amil Ashok, 1979-
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Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Henry I. Smith.
Terms of use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582
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Abstract
Three-dimensional photonic crystals hold tremendous promise toward the realization of truly integrated photonic circuits on a single substrate. Nanofabrication techniques currently limit the ability to create the multilayer structure of dielectric materials. Past investigators have approached the problem using the layer-by-layer fabrication method; this method leverages the planar processes that have been developed by the semiconductor industry. Ultimately, the result from this path offered a small area with low yield and exorbitant costs in terms of time and resources. We introduce large-area membrane stacking as a new approach for three-dimensional nanofabrication. Silicon-nitride membranes are pre-patterned with the two-dimensional photonic crystals. The membranes can then assembled in a serial manner on a substrate to generate the three-dimensional photonic crystal. The efficacy of this method is founded upon the ability to inspect membranes before assembly; it also requires a large yield for stacking. This thesis is concerned with addressing the key challenges of the membranes-tacking- nanofabrication architecture. We develop a process for generating large-area- silicon-nitride membranes and investigate emerging lithography techniques for patterning them: nano-imprint lithography and coherent diffraction lithography. We demonstrate the ability to reliably bond these membranes to a new substrate. Finally, we address the novel problem of releasing the membrane from its frame. This is accomplished by designing stress-engineered cleavage points that detach the membrane while leaving behind defined edges and a particle-free surface. We will show the stacking of two large-area membranes on a patterned substrate for a total of three functional layers.
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
 
Cataloged from PDF version of thesis.
 
Includes bibliographical references (p. 157-163).
 
Date issued
2010
URI
http://hdl.handle.net/1721.1/60175
Department
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

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  • Electrical Engineering and Computer Sciences - Ph.D. / Sc.D.
  • Electrical Engineering and Computer Sciences - Ph.D. / Sc.D.

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