Design and analysis of reconfigurable analog system

Abstract

A highly-configurable analog system is presented. A prototype chip is fabricated and an ADC and filter functionalities are demonstrated. The chip consists of eight identical programmable stages. In an ADC configuration, the first five stages are programmed to implement a 10- bit ADC. The ADC has ENOB of 8 bits at 50 MSPS. The ENOB improves to 8.5 bits if the sampling rate is lowered to 30MSPS. The ADC has an FOM of 150fJ/conversionstep, which is very competitive with the state of the art ADCs. The first stage is responsible for 75% of the input-referred noise power. The sampling noise is responsible for 40% of the total noise power and the zero-crossing detector is responsible for 60%. The chip is tested in two different filter configurations. In one test, the first two stages of the chip are configured as a second order Butterworth filter and the third stage is configured as an amplifier. In another test, the first three stages of the chip are programmed as a third-order Butterworth filter. The desired filter functionalities are demonstrated in both configurations. It is shown that in a third order Butterworth filter, more than 90% of the noise is due to the zero-crossing detector of the last stage. This is mainly due to the fact that the noise of earlier stages is filtered with the filter transfer function, but the noise of the last stage is not filtered. The ZCBC architecture has been used to avoid the stability problems and scale power consumption with sampling frequency. A new technique is introduced to implement the terminating resistors in a ladder filter. This technique does not have any area or power overhead. An asymmetric differential signaling is also introduced. This method improves the dynamic range of the output signals, which is particularly important in new technology nodes with low supply voltage.