Hole mobility in strained Ge/relaxed SiGe with a High-k/metal gate stack

Abstract

The need for high speed and density in the modem semiconductor industry requires new channel materials and techniques for improved carrier transport and continuous scaling of the device dimensions. As a material for enhanced hole transport strained-Ge is implemented in this work. High-k dielectric and metal gate stack is used for improved electrostatic control, as an alternative to the unstable native oxides. The hole mobility of strained-Ge ring-FETs with and without Si cap and with A12 0 3/WN gate stack is investigated. The dependence of the mobility on the strained-Ge layer thickness and the silicon cap thickness is explored. Decrease of 13 % in the hole mobility is observed in the devices with thicker Ge channel suggesting partial relaxation of the strained-Ge. Removal of the Si cap results in almost 40 % decrease in hole mobility suggesting that the presence Si cap is required in realizing high mobility devices.