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An on-chip test circuit for characterization of MEMS resonators

Author(s)
Lee, John Haeseon
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Alternative title
On-chip test circuit for characterization of microelectromechanical systems resonators
Other Contributors
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Duane S. Boning.
Terms of use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582
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Abstract
There has been much interest in developing microelectromechanical systems (MEMS) resonators that achieve comparable performance to traditional resonators yet have smaller footprint and are compatible with CMOS. Recently, MEMS resonators have been proposed that overcome physical limitations in traditional resonators to reach frequencies in the GHz range and that have the potential for compatibility with CMOS, opening up possibilities for new circuits and systems. As with other semiconductor devices, with increasing frequency and with decreasing device size into the submicron scale, variability has started to become a critical issue in MEMS resonators, and thus vigorous characterization of important device parameters has become necessary. This project proposes an on-chip test circuit that can accurately characterize a large number of resonators for variation analysis and is general enough that it can be used with a wide range of resonators, not limited to specific frequencies or other properties. The proposed test circuit is based on a transient impulse response method using a current impulse that excites the resonator under test. The resonator decay behavior is used to accurately measure the series and parallel resonant frequencies and quality factors of the device. The circuit employs a sub-sampling technique that allows measurement and multiplexing of the high-frequency decay signal. A sub-sampling clock generation architecture is proposed that is not based on delay-locked loops, simplifying the design. Finally, a voltage-controlled oscillator (VCO) based analog-to-digital converter (ADC) is implemented on-chip that converts the measured signal into digital codes enabling complete digital interface, which is an important feature for test automation. Simulation shows extraction error less than 100 ppm and 1% for series resonant frequency and series quality factor extraction, respectively.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
 
Cataloged from PDF version of thesis.
 
Includes bibliographical references (p. 93-96).
 
Date issued
2011
URI
http://hdl.handle.net/1721.1/66034
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

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