Design port and optimization of a high-speed SAR ADC comparator from 65nm to 0.11[mu]M
Author(s)Micheva, Nora Iordanova
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Charles G. Sodini and Doris L.
MetadataShow full item record
As the world continues to do more and more of its signal processing digitally, there is an ever increasing need for high speed high precision signal processors in consumer applications such as digital photography. Technological progress in CMOS fabrication has allowed chips to be made on nano scale processes, but this still comes at a steep price. Especially in chips for which analog components are a priority over digital components, some of the benefits of using nano scale processes diminish, such as smaller area. In these cases, it is worth investigating whether the same performance can be achieved with larger feature size, and therefore, cheaper processes. To that end, a three-stage comparator circuit for use in a digital camera SAR ADC has been ported from its original 65nm process to a 0.11[mu]m process. Its design has been analyzed and performance presented here. Additionally, an alternative latch-only architecture for the comparator has been designed and analyzed. In 0.11[mu]m the three-stage comparator operates at the same speed, 13% lower RMS noise contributing 0.9 bits difference, and 11% higher power than the original in 65nm. More noteworthy, the 0.11[mu]m latch-only comparator operates at 40% higher speed, equivalent noise, and 72% lower power.
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2011."May 2011." In title on title page, "[mu]" appears as lower case Greek letter. Cataloged from PDF version of thesis.Includes bibliographical references (p. 50-51).
DepartmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.