Show simple item record

dc.contributor.authorKeckler, Stephen W.en_US
dc.date.accessioned2004-10-20T19:57:35Z
dc.date.available2004-10-20T19:57:35Z
dc.date.issued1992-09-01en_US
dc.identifier.otherAITR-1355en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/6807
dc.description.abstractThis report describes Processor Coupling, a mechanism for controlling multiple ALUs on a single integrated circuit to exploit both instruction-level and inter-thread parallelism. A compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle byscycle basis, and several threads can be active concurrently. Simulation results show that Processor Coupling performs well both on single threaded and multi-threaded applications. The experiments address the effects of memory latencies, function unit latencies, and communication bandwidth between function units.en_US
dc.format.extent165 p.en_US
dc.format.extent19986107 bytes
dc.format.extent16194697 bytes
dc.format.mimetypeapplication/postscript
dc.format.mimetypeapplication/pdf
dc.language.isoen_US
dc.relation.ispartofseriesAITR-1355en_US
dc.subjectruntime schedulingen_US
dc.subjectcompile time schedulingen_US
dc.subjectparallelscomputersen_US
dc.subjectmultithreadingen_US
dc.titleA Coupled Multi-ALU Processing Node for a Highly Parallel Computeren_US


Files in this item

Thumbnail
Thumbnail

This item appears in the following Collection(s)

Show simple item record