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Test Generation Guided Design for Testability

Author(s)
Wu, Peng
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Abstract
This thesis presents a new approach to building a design for testability (DFT) system. The system takes a digital circuit description, finds out the problems in testing it, and suggests circuit modifications to correct those problems. The key contributions of the thesis research are (1) setting design for testability in the context of test generation (TG), (2) using failures during FG to focus on testability problems, and (3) relating circuit modifications directly to the failures. A natural functionality set is used to represent the maximum functionalities that a component can have. The current implementation has only primitive domain knowledge and needs other work as well. However, armed with the knowledge of TG, it has already demonstrated its ability and produced some interesting results on a simple microprocessor.
Date issued
1988-07-01
URI
http://hdl.handle.net/1721.1/6837
Other identifiers
AITR-1051
Series/Report no.
AITR-1051
Keywords
artificial intelligence, knowledge representation, testsgeneration, knowledge-based systems, VLSI design for testability

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