Scratching by pad asperities in chemical mechanical polishing

Abstract

The exponential increase through time in the number of components in a typical integrated circuit, known as Moore's Law, is driving the need for improvements in manufacturing. A key semiconductor manufacturing process is chemical-mechanical polishing (CMP), which is used to create connecting metal channels above the transistors in a chip. A typical form of this process used in industry is metal CMP. Metal CMP is the process of using a pad combined with an abrasive slurry to remove excess material, such as Cu, and planarize a surface. The continuing trend to increase the number of components per chip leads to the necessity of Cu features being increasingly small. This increases the resistance of each copper connection, leading to an increase in the RC time delay of each circuit. To counteract the increase in resistance, the use of low dielectric constant (k) materials in place of SiO₂ has been explored. Low-k dielectrics are much softer than SiO₂, which has led to problems with scratching of the Cu during CMP, resulting in faulty parts. Recent research by Thor Eusner indicates that the pad used to polish the surface, not the abrasives in the slurry, may be responsible for the scratching of the Cu surface. This thesis applies this pad asperity scratching model to several CMP pads. The most relevant parameters to scratching, pad to copper hardness ratio and the coefficient of friction, are measured for each pad and the results indicate that scratching should be a problem with nearly all of the pads. This indicates that current CMP pads or slurries are too hard, have too much friction, have asperities that are too sharp, or some combination of these factors. Reengineering CMP pads and slurries is thus recommended to alleviate scratching by pad asperities.