Analytical model for RF power performance of deeply scaled CMOS devices
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This paper presents a first order model for RF power of deeply scaled CMOS. The model highlights the role of device on-resistance in determining the maximum RF power. We show excellent agreement between the model and the measured data on 45 nm CMOS devices across a wide range of device widths, under both maximum output power and maximum PAE conditions. The model allows circuit designers to quickly estimate the power and efficiency of a device layout without need for complicated compact models or simulations.
Date issued
2011-07Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer ScienceJournal
2011 IEEE Radio Frequency Integrated Circuits Symposium
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Citation
Gogineni, Usha, Jesus del Alamo, and Alberto Valdes-Garcia. “Analytical Model for RF Power Performance of Deeply Scaled CMOS Devices.” IEEE Radio Frequency Integrated Circuits Symposium, 2011. 2011 1–4.
Version: Author's final manuscript
ISBN
978-1-4244-8291-7
978-1-4244-8293-1
ISSN
1529-2517