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dc.contributor.authorLis, Mieszko
dc.contributor.authorShim, Keun Sup
dc.contributor.authorCho, Myong Hyon
dc.contributor.authorDevadas, Srinivas
dc.date.accessioned2012-09-07T19:35:51Z
dc.date.available2012-09-07T19:35:51Z
dc.date.issued2011-11
dc.date.submitted2011-10
dc.identifier.isbn978-1-4577-1953-0
dc.identifier.issn1063-6404
dc.identifier.urihttp://hdl.handle.net/1721.1/72582
dc.description.abstractAs we enter an era of exascale multicores, the question of efficiently supporting a shared memory model has become of paramount importance. On the one hand, programmers demand the convenience of coherent shared memory; on the other, growing core counts place higher demands on the memory subsystem and increasing on-chip distances mean that interconnect delays are becoming a significant part of memory access latencies. In this article, we first review the traditional techniques for providing a shared memory abstraction at the hardware level in multicore systems. We describe two new schemes that guarantee coherent shared memory without the complexity and overheads of a cache coherence protocol, namely execution migration and library cache coherence. We compare these approaches using an analytical model based on average memory latency, and give intuition for the strengths and weaknesses of each. Finally, we describe hybrid schemes that combine the strengths of different schemes.en_US
dc.language.isoen_US
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en_US
dc.relation.isversionofhttp://dx.doi.org/10.1109/ICCD.2011.6081367en_US
dc.rightsCreative Commons Attribution-Noncommercial-Share Alike 3.0en_US
dc.rights.urihttp://creativecommons.org/licenses/by-nc-sa/3.0/en_US
dc.sourceMIT web domainen_US
dc.titleMemory coherence in the age of multicoresen_US
dc.typeArticleen_US
dc.identifier.citationLis, Mieszko et al. “Memory Coherence in the Age of Multicores.” IEEE 29th International Conference on Computer Design 2011 (ICCD). 1–8.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.contributor.approverDevadas, Srinivas
dc.contributor.mitauthorLis, Mieszko
dc.contributor.mitauthorShim, Keun Sup
dc.contributor.mitauthorCho, Myong Hyon
dc.contributor.mitauthorDevadas, Srinivas
dc.relation.journalIEEE 29th International Conference on Computer Design 2011 (ICCD)en_US
dc.eprint.versionAuthor's final manuscripten_US
dc.type.urihttp://purl.org/eprint/type/ConferencePaperen_US
dspace.orderedauthorsLis, Mieszko; Shim, Keun Sup; Cho, Myong Hyon; Devadas, Srinivasen
dc.identifier.orcidhttps://orcid.org/0000-0001-8253-7714
mit.licenseOPEN_ACCESS_POLICYen_US


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