Circuit implementations for high-efficiency video coding tools

Author(s)
Tikekar, Mehul (Mehul Deepak)
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Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Anantha P. Chandrakasan.
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Abstract
High-Efficiency Video Coding (HEVC) is planned to be the successor video standard to the popular Advanced Video Coding (H.264/AVC) with a targeted 2x improvement in compression at the same quality. This improvement comes at the cost of increased complexity through the addition of new coding tools and increased computation in existing tools. The ever-increasing demand for higher resolution video further adds to the computation cost. In this work, digital circuits for two HEVC tools - inverse transform and deblocking filter are implemented to support Quad-Full HD (4K x 2K) video decoding at 30fps. Techniques to reduce power and area cost are investigated and synthesis results in 40nm CMOS technology and Virtex-6 FPGA platform are presented.
Description
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
 
Cataloged from PDF version of thesis.
 
Includes bibliographical references (p. 71-72).
 
Date issued
2012
URI
http://hdl.handle.net/1721.1/75691
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.
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