Pipelined oversampling analog-to-digital converters

Abstract

Oversampling and noise-shaping techniques, such as [delta sigma] modulation, are widely used in analog-to-digital conversion to achieve accuracy that exceeds that of integrated-circuit components. Such converters have an inherent tradeoff between accuracy and speed, whereby resolution in amplitude is achieved at the expense of resolution in time. Although much attention has been focused on improving the speed and power of [delta sigma] analog-to-digital converters, data rates remain limited to less than a few MHz and are not easily extended. A pipelined oversampling architecture is described that circumvents the speed-resolution tradeoff of conventional oversampling converters by performing spatial, rather than temporal, oversampling. It combines high-resolution capabilities of [delta sigma] techniques with the high speed of pipelined architectures so that both of these attributes are achievable. The architecture also differs from conventional oversampling in that it performs Nyquist-rate sampling. Power is improved as a result of a charge-domain implementation, reduced sensitivity to thermal noise, simplified decimation, and reduced circuit speed, which permits voltage scaling and use of low-power technologies. Circuit techniques for implementation of a pipelined oversampling converter are also presented. Although CCDs are not essential to the concept, such converters are most practically built using a combination of CCD and CMOS circuits. CCDs make analog pipelines with hundreds of stages feasible by providing fully-depleted operations which are highly accurate, low power, simple, and compact. Other operations are performed using nondepleted circuits.

(cont.) A circuit technique, referred to as dynamic double sampling, is presented, which provides improved linearity and speed over existing techniques and forms a core circuit element for these nondepleted operations. Two prototype converters have been demonstrated. They were built in standard CMOS processes and show that moderate to high performance is possible from CCD circuits and can be achieved without custom processing. The first prototype uses a 1.2-[mu]m process and operates at an 18-MHz data rate. It achieves 78-dB SFDR, DNL < ±0.15 LSB at 13 bits, 74-dB SNR over a 9-MHz bandwidth, and 324 mW power dissipation. The second prototype uses a 0.6-[mu]m design rule and operates at a 30-MHz data rate. It achieves 70-dB SFDR and 66-dB SNR over a 15-MHz bandwidth.