Investigation of the electron transport and electrostatics of nanoscale strained Si/Si/Ge heterostructure MOSFETs

Abstract

This thesis presents work aimed at investigating the possible benefit of strained-Si/SiGe heterostructure MOSFETs designed for nanoscale (sub-50-nm) gate lengths with the aid of device fabrication and electrical measurements combined with computer simulation. MOSFET devices fabricated on bulk-Si material are scaled in order to achieve gains in performance and integration. However, as device dimensions continue to scale, physical constraints are being reached that may limit continued scaling and/or the gains in performance from scaling. In order to continue the benefits of scaling, a possible solution is to change to a strained-Si/SiGe material system where enhanced electron mobility of 1.7-2X has been demonstrated for long-channel n-type devices. The electron mobility enhancement observed for long channel length devices may not be the same for devices with nanoscale gate length. In particular, increased channel doping, which is required to control short-channel effects can result in degraded transport characteristics. In this work, the impact of high channel doping on mobility enhancements in strained-Si n-MOSFETs is investigated experimentally. Increased channel doping will increase Coulomb scattering interactions increasing its influence on the overall mobility. Electron transport models were calibrated using experimental data for both strained and un-strained Si devices for various channel doping concentrations. The transport models were then used to investigate, by computer simulation, the performance enhancement of nanoscale strained Si devices for equivalent off-current.