Comprehensive inverse modeling for the study of carrier transport models in sub-50nm MOSFETs

Abstract

Direct quantitative 2-D characterization of sub-50 nm MOSFETs continues to be elusive. This research develops a comprehensive indirect inverse modeling technique for extracting 2-D device topology using combined log(I)-V and C-V data. An optimization loop minimizes the error between a broad range of simulated and measured electrical characteristics by adjusting parameterized profiles. The extracted profiles are reliable in that they exhibit decreased RMS error as the doping parameterization becomes increasingly comprehensive of doping features. The inverse modeling methodology pieces together complementary MOSFET data sets such as capacitance of the gate stack, 1-D doping analysis, subthreshold I-V which is a strong function of 2-D doping, and C-V data which is especially sensitive to the source/drain. Combining the data sets enhances the extracted profiles. Such profiles serve as a basis for tuning diffusion coefficients in order to realistically calibrate modern process simulators.

(cont.) The important application of this technique is in the calibration of carrier transport models. With an accurate device topology, the transport model parameters can be adjusted to predict the onstate behavior. Utilizing a mobility model that conforms to the experimental effective field dependence and including a correction for parasitic resistance, the transport model for an advanced NMOS generation at various gate lengths and voltages is calibrated. Employing the Energy Balance model yields an energy relaxation value valid over all devices examined in this work. Furthermore, what has been learned from profile and transport calibration is used in investigating optimal paths for sub-20 nm MOSFET scaling. In a study of candidate architectures such as double-gate, single-gate, and bulk-Si, metrics for the power versus performance trade-off were developed. To conclude, the best trade-off was observed by scaling as a function of gate length with a single near-mid-gap workfunction.