Superlattice-source nanowire FET with steep Subthreshold characteristics

Abstract

The non-scalable room temperature 60 mV/dec subthreshold swing of a conventional MOSFET is a fundamental limit to the continuation of transistor power scaling. In order to further reduce transistor power consumption and transistor footprint, new subthreshold transport mechanisms other than thermionic emission over an energy barrier are required. In this thesis, we devote our efforts towards the analysis and demonstration of a superlattice-source nanowire FET which can potentially beat the 60 mV/dec limit. This key to this device concept is to engineer the density of states of electrons at the source via a superlattice. We have calculated the band structure of a superlattice using a self-consistent quantum-mechanical simulation environment. In particular, the effect of transversal confinement on the band structure of a superlattice that occurs in a nanowire has been studied. We show that in order to obtain single-subband conduction, semiconductor nanowires with sub-10 nm diameter have to be fabricated. An analytical expression of the subthreshold swing including the effect of band edges has been derived and good agreement with simulations was achieved. A process flow to fabricate III-V nanowire MOSFETs has been designed. We have developed several key aspects of this process and have demonstrated the capability of fabricating smooth high-aspect ratio sub-10 nm semiconductor pillars in the InGaAs/InAlAs system lattice matched to InP.