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dc.contributor.advisorMarc A. Kastner.en_US
dc.contributor.authorEasley, Justin Lavaughnen_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Physics.en_US
dc.date.accessioned2014-01-23T18:40:49Z
dc.date.available2014-01-23T18:40:49Z
dc.date.issued2013en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/84389
dc.descriptionThesis (S.B.)--Massachusetts Institute of Technology, Dept. of Physics, 2013.en_US
dc.descriptionCataloged from PDF version of thesis.en_US
dc.descriptionIncludes bibliographical references (page 31).en_US
dc.description.abstractIn this thesis, I fabricated and tested p-channel dual gate MOSFETs that will be used to make conductance and resistance measurements of nanocrystalline solids. Using MOSFETs with narrow gates, we can measure the resistance of these nanocrystals, which are typically extremely high. The group had previously used n-channel MOSFETs, and this project tests the potential for using p-channel devices. This thesis discusses the fabrication techniques and challenges, as well as G-Vg, threshold voltage, and hole mobility measurements from wide gate devices, which are used as a proof of concept for the narrow gate devices. Future work in the group will finish fabricating and testing narrow gate devices.en_US
dc.description.statementofresponsibilityby Justin Lavaughn Easley.en_US
dc.format.extent31 pagesen_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectPhysics.en_US
dc.titleFabrication and testing of dual gate p-channel MOSFETsen_US
dc.typeThesisen_US
dc.description.degreeS.B.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Physics
dc.identifier.oclc867649970en_US


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