High mobility strained Si/SiGe heterostructure MOSFETs : channel engineering and virtual substrate optimization

Abstract

High quality relaxed silicon-germanium graded buffers are an important platform for monolithic integration of high speed heterostructure field-effect transistors and III-V-based optoelectronics onto silicon substrates. In this thesis, dislocation dynamics in compositionally graded SiGe layers are explored and mobility enhancements in strained Si/SiGe metal-oxide-semiconductor field-effect transistors (MOSFETs) are evaluated. These results demonstrate the dramatic increases in microelectronics performance and functionality that can be obtained through use of the relaxed SiGe integration platform. By extending and modifying a model for dislocation glide kinetics in graded buffers to SiGe/Si, a complete picture of strain relaxation in SiGe graded buffers emerges. To investigate dislocation glide kinetics in these structures, a series of identical samples graded to 30% Ge have been grown at temperatures between 650ʻC and 900ʻC on (001)-, (001) offcut 6ʻ towards an in-plane <110>-, and (001) offcut 6ʻ towards an in-plane <100>-oriented Si substrates. The evolution of field threading dislocation density (TDD) with growth temperature in the on-axis samples indicates that dislocation nucleation and glide kinetics together control dislocation density in graded buffers. The TDD of samples grown on offcut substrates exhibits a more complicated temperature dependence, due to their reduced tendency towards dislocation pile-up formation at low temperature and dislocation reduction reactions at high temperature. Finally, by evaluating field threading dislocation density and dislocation pile-up density in a wide variety of SiGe graded buffers, a correlation between dislocation pile-up formation and increases in field threading dislocation density emerges.

(cont.) Record mobility strained Si p-MOSFETs have been fabricated on relaxed 40% Ge virtual substrates. Hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with mobility enhancements over twice that of co-processed bulk Si devices. In contrast, hole mobility in strained Si p-MOSFETs displays no strong dependence on strained layer thickness. These results indicate that strain is the primary variable in determining hole mobility in strained Si p-MOSFETs and that symmetric electron and hole mobility enhancements in strained Si MOSFETs can be obtained for virtual substrate compositions beyond 35% Ge. The effect of alloy scattering on carrier mobility in tensile strained SiGe surface channel MOSFETs is measured directly for the first time. Electron mobility is degraded much more severely than hole mobility in these heterostructures, in agreement with theoretical predictions. Dual channel heterostructures, which consist of the combination of buried compressively strained SiilyGey buried channels and tensile strained Si surface channels, grown on relaxed SilxGex virtual substrates, are explored in detail for the first time. Hole mobilities exceeding 700 cm2/V-s have been achieved by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. This layer sequence exhibits nearly symmetric electron and hole mobilities, both enhanced relative to bulk Si ...