Selective SiGe nanostructures
Author(s)Langdo, Thomas Andrew, 1974-
Massachusetts Institute of Technology. Dept. of Materials Science and Engineering.
Eugene A. Fitzgerald.
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Selective epitaxial growth (SEG) of SiGe on patterned SiO2/Si substrates by ultra-high vacuum chemical vapor deposition (UHVCVD) shows promise for the fabrication of novel SiGe microelectronic structures. This work explores selective growth conditions in the SiH2Cl2/SiH4/GeH4/H2 system between 650-850⁰C, without the addition of C12 or HC1, on substrates patterned by both conventional and interferometric lithography. We have achieved several important milestones for the fabrication of vertical MOSFETs by selective growth in 100 nm SiO2 features patterned by interferometric lithography. We have observed excellent selectivity to SiO2 masks with SiH2C12 at 750⁰C, perfect epitaxial Si filling of SiO2 features, the facet morphology during growth, and the effects of n-type doping on selective growth. We have also fabricated extremely sharp p-n diode doping profiles. With the above accomplishments we have demonstrated the feasibility of vertical MOSFET fabrication through selective epitaxial growth. To realize the advantages of advanced MOSFET designs on silicon-on-insulator (SOI) substrates, we have developed a facet-free raised source/drain process utilizing moderate n-type doping of Si selective growth and <110>-oriented vertical SiO2 sidewalls. However, to improve SiO2 spacer dimension fidelity and eliminate Si substrate overetching, a novel SiO2/Si3N4 spacer process was developed. The keys to the SiO2/Si3N4 spacer process are removal of the Si3N4 layer prior to growth and increased Si ELO growth by moderate in situ n-type doping. This process has wide ranging application to both SOI and bulk Si technologies for fabrication of low-resistance contacts in advanced devices.(cont.) By a combination of interferometric lithography Si/SiO2 substrate patterning and Ge selective epitaxial growth, we have demonstrated threading dislocation blocking at the oxide sidewall which shows promise for dislocation filtering and the fabrication of low defect density Ge on Si for III-V device integration. Defects at the Ge film surface only arise at the merging of epitaxial lateral overgrowth (ELO) fronts from neighboring holes. These results confirm that epitaxial necking can be used to reduce threading dislocation density in any lattice-mismatched systems where dislocations are not parallel to growth directions. Investigation of Ge selective growth in micron-sized SiO2 features by plan-view TEM shows that substrate patterning on the order of microns is insufficient to filter dislocations in a large mismatch system ([epsilon] > 2%). Ge p-i-n photodetectors were selectively grown in micron-sized SiO2/Si features to correlate materials properties with electrical characteristics. For chemical protection and compatibility with Si microelectronics, Ge photodetector regions were capped with a thin n+ Si layer. Photodetectors fabricated on unpatterned substrates demonstrated leakage currents comparable to published results on Ge on Si photodetectors while leakage currents were noticeably degraded in devices grown on patterned substrates.
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2001.Includes bibliographical references (p. 206-215).
DepartmentMassachusetts Institute of Technology. Dept. of Materials Science and Engineering.
Massachusetts Institute of Technology
Materials Science and Engineering.