Low-energy radix-2 serial and parallel FFT designs

Abstract

The push for portable electronics for communication and biomedical applications has accelerated the growing momentum for high performance and low energy hardware implementations of the Fast Fourier Transform (FFT). This work presents several new hardware implementations of the radix-2 FFT algorithms that take advantage of intermittent data and parallelism to reduce the energy per FFT. In the modified serial design, by using a low-power control memory and a pipelined data look-ahead controller to optimize processing of sequences of data with zeros, up to 45% of energy savings are achieved as compared to the baseline design. Two fully parallel FFTs with different datapaths are also developed based on a FFT flow diagram with the same geometry in each stage. Energy savings of up to 90% (an order of magnitude) are achieved as compared to the baseline design. These results are demonstrated through post-layout and parasitic extraction Nanosim simulations with 90nm standard cell libraries.