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Parallelized two-stage object detection in cluttered RGB-D scenes

Author(s)
Popović, Sanja, M. Eng. Massachusetts Institute of Technology
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Parallelized 2-stage object detection in cluttered RGB-D scenes
Other Contributors
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Advisor
Leslie Pack Kaelbling and Tomás Lozano-Pérez.
Terms of use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/7582
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Abstract
Modern graphics hardware (GPUs) are an amazing computational resource, but only for algorithms with suitable structure. Computer vision algorithms have many characteristics in common with computer graphics algorithms, in particular, they repeat some operations, such as feature computations, at many places in the image. However, there are also more global operations, such as finding nearest neighbors in feature space, that present more of a challenge. In this thesis, we showed how a state-of-the-art object detector, based on RGB-D images, could be parallelized for use on GPUs. By using nVidia's CUDA platform we improved the running times of critical sections up to 38 times. We also built a two-stage pipeline that improves multiple object detection in cluttered scenes. The first stage aims to achieve high precision, even at the cost of lower recall, by detecting only the less occluded objects. This results in large fraction of the scene being labeled which enables the algorithm in the second stage to focus on the less visible objects that would otherwise be missed. We analyze the performance of our algorithm and lay grounds for the future work and extensions.
Description
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2013.
 
Cataloged from PDF version of thesis.
 
Includes bibliographical references (pages 40-41).
 
Date issued
2013
URI
http://hdl.handle.net/1721.1/85466
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

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