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dc.contributor.advisorDimitri A. Antoniadis.en_US
dc.contributor.authorLochtefeld, Anthony Joseph, 1965-en_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2005-08-23T21:20:00Z
dc.date.available2005-08-23T21:20:00Z
dc.date.copyright2001en_US
dc.date.issued2001en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/8567
dc.descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.en_US
dc.descriptionIncludes bibliographical references (p. 126-133).en_US
dc.description.abstractMOSFET scaling and performance has progressed rapidly in recent years, with physical gate lengths for electrostatically sound devices reaching 30 nm or below: near the prospective scaling limits for traditional bulk MOSFETs. This work investigates several key issues for this "end of roadmap" regime. Focus is on understanding the limitations to carrier velocity in MOSFET inversion layers as channel lengths are scaled well below 100 nm, and on relaxing these limits through architectural alternatives to bulk MOSFETs. It has been proposed that drain current is ultimately limited by the rate at which carriers can be thermally injected from the source into the channel. In this work it is shown that commonly used techniques for experimentally determining carrier velocity are insufficient to determine how close modem MOSFETs operate to this ballistic or "thermal limit". A new technique is proposed, and applied to two advanced industry technologies with deep-sub-100-nm channel lengths. It is shown that a IV NMOS technology with Leff < 50 nm operates at no more than -40% of the limiting thermal velocity. Furthermore, no indication is found that continued scaling is bringing us closer to the thermal velocity limit. Via simulation, the relationship between mobility and scaling is investigated for bulk silicon NMOSFETs and FDSOI (Fully-Depleted Silicon-On-Insulator) alternatives, focusing on the 50 and 25 nm Leff generations. Scaling of bulk MOSFETs well below 100 nm Leff requires heavy channel doping, leading to degraded low-field mobility. Provided that the gate workfunction is used to determined the threshold voltage, FDSOI devices do not suffer from this trade-off, by virtue of the fact that their channel can be undoped. It is shown that single-gate FDSOI is, accordingly, an attractive alternative down to 50 nm Leff. For deeper scaling, double-gate FDSOI should have approximately a 3X mobility advantage over bulk NMOS. With careful determination of channel length, inversion-layer charge, and series resistance, it is possible to study experimentally the relation between channel length and mobility in deep-sub- 100-nm MOSFETs. With the aid of inverse modeling techniques, evidence is found that in the very shortest modern MOSFETs, mobility is less then would be expected from "universal" mobility, and independent of transverse field. This may be indicative of a transition in the dominant scattering mechanism, from surface- to Coulomb- scattering. The relevance of low-field mobility to the performance of deep-sub-100-nm MOSFETs is not well understood. In this work this relationship is studied experimentally: mobility (with low lateral electric field) is modified by externally applying uniaxial stress to NMOS devices, and the corresponding shift in carrier velocity (with high lateral field) is measured. The dependence of velocity on mobility is found to be significant, and is found to correspond well with the predictions of energy-balance modeling. Given their promise for scalability without mobility degradation, the design space for FDSOI MOSFETs merits detailed study. Via 2D simulation, scalability and drive current are investigated for three basic FDSOI alternatives: single-gate, and double-gate either with symmetrical workfunction mid-gap gates or asymmetrical workfunction n+p+ gates. For the single-gate device, it is shown that scaling below Leff = 35 nm may not be achievable for practical silicon film thickness, unless Ioff requirements are relaxed. For double-gate devices we have shown that hypothetical mid-gap top- and bottom- gates are superior to n+/p+ poly gates, for both scalability and drive current. Realization of the ideal double-gate device structure involves three major technical challenges: formation of gates above and below a thin single-crystalline silicon layer, achievement of fine alignment between top- and bottom-gates, and achieving low source/drain resistance for the thin silicon film. These issues are addressed in this work through demonstration of three primary technologies: wafer bonding with pre-patterned features, interferometric alignment, and selective epitaxy for raised source/drains.en_US
dc.description.statementofresponsibilityby Anthony Joseph Lochtefeld.en_US
dc.format.extent136 p.en_US
dc.format.extent9518908 bytes
dc.format.extent9518667 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleToward the end of the MOSFET roadmap : investigating fundamental transport limits and device architecture alternativesen_US
dc.title.alternativeToward the end of the metal oxide semiconductor field-effect transistor roadmapen_US
dc.typeThesisen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.identifier.oclc49201716en_US


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