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dc.contributor.advisorDuane S. Boning.en_US
dc.contributor.authorMehrotra, Vikas, 1971-en_US
dc.contributor.otherMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2014-05-07T16:56:44Z
dc.date.available2014-05-07T16:56:44Z
dc.date.copyright2001en_US
dc.date.issued2001en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/86666
dc.descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.en_US
dc.descriptionIncludes bibliographical references (p. 151-156).en_US
dc.description.statementofresponsibilityby Vikas Mehrotra.en_US
dc.format.extent156 p.en_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582en_US
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleModeling the effects of systematic process variation of circuit performanceen_US
dc.typeThesisen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.en_US
dc.identifier.oclc49201651en_US


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