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dc.contributor.advisorHae-Seung (Harry) Lee.en_US
dc.contributor.authorGulati, Kushen_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2005-08-23T22:28:35Z
dc.date.available2005-08-23T22:28:35Z
dc.date.copyright2001en_US
dc.date.issued2001en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/8701
dc.descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.en_US
dc.descriptionIncludes bibliographical references (p. 197-200).en_US
dc.description.abstractThis thesis presents the concept, theory and design of a low power CMOS analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption. The converter achieves the wide operating range by reconfiguring (1) its architecture between pipeline and delta-sigma modes (2) by varying its circuit parameters such as size of capacitors, length of pipeline, oversampling ratio, among others and (3) by varying the bias currents of the opamps in proportion with converter sampling frequency, accomplished through the use of a phase-locked loop. Target input signals for this ADC include high frequency and moderate resolution signals such as video and low I.F. in radio Receivers, low frequency and high resolution signals from seismic sensors and MEMs devices, and others that fall in between these extremes such as audio, voice and general purpose data-acquisition. This converter also incorporates several power reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design.en_US
dc.description.abstract(cont.) At a converter power supply at 3.3V, the converter achieves a bandwidth range of 0-10MHz over a resolution range of 6 -16 bits, and parameter reconfiguration time of 12 clock cycles. Its PLL lock range is measured at 20KHz to 40MHz. In the delta-sigma mode, it achieves a maximum SNR of 94dB and second and third harmonic distortions of 102dB and 95dB, respectively at 10MHz clock frequency, 9.4KHz bandwidth, and 17.6mW power. In the pipeline mode, it achieves a maximum DNL and INL of +/-0.55LSBs and +/-0.82LSBs, respectively, at 11-bits of resolution, at a clock frequency of 2.6MHz and 1MHz tone with 24.6mW of power.en_US
dc.description.statementofresponsibilityby Kush Gulati.en_US
dc.format.extent200 p.en_US
dc.format.extent15127453 bytes
dc.format.extent15127213 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleA low-power reconfigurable analog-to-digital converteren_US
dc.typeThesisen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc49839428en_US


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