Smart IP of QR decomposition for rapid prototyping on FPGAs

Abstract

The Digital Signal Processing (DSP) systems used in mobile wireless communication, such as MIMO detection, beam formation in smart antennas, and compressed sensing, all rely on quickly solving linear systems of equations. These applications of DSP have vastly different throughput, latency and area requirements, necessitating substantially different hardware solutions. The QR decomposition (QRD) method is an efficient way of solving linear equation systems using specialized hardware, and is known to be numerically stable [17]. We present the design and FPGA implementation of smart IP (intellectual property) for QRD based on Givens-Rotation (GR) and Modified-Gram- Schmidt (MGS) algorithms. Our configurable designs are flexible enough to meet a wide variety of application requirements. We demonstrate that our area and timing results are comparable, and in some cases superior, to state-of-art hardware-based QRD implementations. Our QRD design based on a Log-domain GR Systolic array achieved a throughput of 10.1M rows/sec for a complex valued 3x3 matrix on Virtex-6 FPGA, whereas our QRD design based on a Log-domain GR Linear array was found to be an area optimized solution requiring the fewest FPGA slices. Overall the Logdomain GR Systolic array implementation was found to be the most resource efficient design (IP for all of our proposed architectures have been prepared and are available at http://saqib.scripts.mit.edu/qr-code.php). Our set of IP can be configured to satisfy variety of application demands, and can be used to generate hardware designs with nearly zero design and debugging time. Moreover the reported results can be used to pick the optimal design choice based on a given set of design requirements. Since our architectures are completely modular, their sub-units can be independently optimized and tested without the need for re-testing the whole system.