Energy-aware system design using circuit reconfigurability with a focus on low-power SRAMs
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Anantha P. Chandrakasan.
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Today's complex systems generally target competing design goals such as maximizing performance while minimizing energy. Moreover, they have to work efficiently under changing system dynamics and application loads. Thus, for better power and performance optimization, they need to adapt to different conditions on-the-fly. In this regard, systems need to monitor important metrics such as energy consumption and performance. First part of this thesis focuses on an energy monitoring circuit design that can generate a digital representation of the absolute energy per operation of a circuit. A test-chip is fabricated in a 65nm LP CMOS process and the energy monitoring circuit is demonstrated for an SRAM application. The small power (< 0.1%) and area overhead (16%) of the energy monitor motivated its usage within a system level application. Next, as a collaboration of circuit designers and architects, energy monitoring is extended to a processor system for system-level power and performance optimizations. To enable self-adaptation, custom blocks in the system are designed to accommodate reconfigurability. In this regard, the data cache is designed to be reconfigurable in terms of set associativity (1-4 sets) and size (1kB to 4kB per set). Furthermore, the system is designed to enable voltage and frequency scaling. Energy monitoring circuits that are capable of monitoring runtime conditions for different domains are embedded into on-chip DC-DC converters. Those ideas are demonstrated in a 0.18pm system-on-chip design and measurement results show that the system can achieve up to 8.4x energy savings. SRAMs account for a large fraction of system area and power. Thus, low-voltage SRAM operation is crucial for an energy-efficient system design. Two SRAM circuits are demonstrated in 65nm and 0.18[mu]m test-chips using 8T bit-cells and write assists, and they are measured to be voltage scalable from 1V to 0.37V and from 1.8V to 0.6V respectively. Secondly, write and read assist techniques are illustrated for an industry sized, 6T bit-cell based SRAM design. A test-chip is fabricated using a cutting-edge 28nm FD-SOI technology and the SRAMs are measured to be operational down to 0.43 V.
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.Cataloged from PDF version of thesis.Includes bibliographical references (pages 183-193).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.