Nano-scale ohmic contacts for III-V MOSFETs
Nano-scale ohmic contacts for 3-5 MOSFETs
Nano-scale ohmic contacts for three-five MOSFETs
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Jesús A. del Alamo
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As modem silicon CMOS has been scaled down to extremely small dimensions, there is an urgent need for technological innovations of new devices architectures that would allow the continuation of Moore's Law into the future. In particular, for CMOS with nanometer scale pitch size, the intrinsic electronic properties of silicon as channel material represent a significant hindrance to further scaling. As a result, new channel materials are being investigated all over the world that would enable the push into the sub-10 nm regime. Among them, certain III-V compound semiconductors have emerged as the most promising candidates to replace silicon in future generations of CMOS. In particular and as a result of their extraordinary electron or hole transport properties, InGaAs, InAs, and InGaSb enable transistors with faster operation at a lower power consumption. This is the key to enable future scaling. One of the major challenges of extremely-scaled III-V logic MOSFETs is the series resistance. To achieve the performance goals, it is necessary to fabricate source and drain ohmic contacts with ultra-low contact resistance, perhaps as low as 50 [Omega] · [mu]m. This is particularly difficult to achieve as the device size shrinks down to the 10-20 nm length range since the contact resistance increases drastically for small contact lengths. Moreover, it is not clearly known how to characterize nano-scale metal-semiconductor ohmic contacts. All available test structures and models, such as the transmission line model (TLM), are designed for relatively large ohmic contacts, on the order of micrometers, and are unable to make accurate measurements of extremely small contact resistance. To deal with nano-scale contacts for III-V CMOS, we need a more accurate test structure capable of extracting extremely small values of contact resistance on very small contacts. In this thesis, a novel test structure, nano-TLM, is developed to address this issue. We demonstrate how the nano-TLM is capable of providing accurate measurements of the contact resistance, metal resistance, and semiconductor resistance of an ohmic contact system at the same time. We demonstrate this new technique in Mo/n⁺-InGaAs ohmic contacts where we have achieved an extremely low contact resistance of 32.5 [Omega] · [mu]m with contact length as small as 19 nm. This contact resistance at this contact length is, to the best of our knowledge, the lowest reported value to date. Our proposed new test structure will help understand and characterize ohmic contacts suitable for future III-V CMOS device fabrication.
Thesis: S.M. in Electrical Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.35Cataloged from PDF version of thesis.Includes bibliographical references (pages 65-68).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.