Energy-efficient SRAM design in 28nm FDSOI Technology

Abstract

As CMOS scaling continues to sub-32nm regime, the effects of device variations become more prominent. This is very critical in SRAMs, which use very small transistor dimensions to achieve high memory density. The conventional 6T SRAM bit-cell, which provides the smallest cell-area, fails to operate at lower supply voltages (Vdd). This is due to the significant degradation of functional margins as the supply voltage is scaled down. However, Vdd scaling is crucial in reducing the energy consumption of SRAMs, which is a significant portion of the overall energy consumption in modern micro-processors. Energy savings in SRAM is particularly important for batteryoperated applications, which run from a very constrained power-budget. This thesis focuses on energy-efficient 6T SRAM design in a 28nm FDSOI technology. Significant savings in energy/access of the SRAM is achieved using two techniques: Vdd scaling and data prediction. A 200mV improvement in the minimum SRAM operating voltage (Vdd,min) is achieved by using dynamic forward body-biasing (FBB) on the NMOS devices of the bit-cell. The overhead of dynamic FBB is reduced by implementing it row-wise. Layout modifications are proposed to share the body terminals (n-wells) horizontally, along a row. Further savings in energy/access is achieved by incoporating data-prediction in the 6T read path, which reduces bitline switching. The proposed techniques are implemented for a 128Kb 6T SRAM, designed in a 28nm FDSOI technology. This thesis also presents a reconfigurable fully-integrated switched-capacitor based step-up DC-DC converter, which can be used to generate the body-bias voltage for a SRAM. 3 reconfigurable conversion ratios of 5/2, 2/1 and 3/2 are implemented in the converter. It provides a wide range of output voltage, 1.2V-2.4V, from a fixed input of 1V. The converter achieves a peak efficiency of 88%, using only on-chip MOS and MOM capacitors, for a high density implementation.