Test structure, circuits and extraction methods to determine the radius of infuence of STI and polysilicon pattern density
Author(s)Chang, Albert H.; Zuo, Kewei; Wang, Jean; Yu, Douglas; Boning, Duane S.
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Advanced CMOS processes need new methodologies to extract, characterize and model process variations and their sources. Most prior studies have focused on understanding the effect of local layout features on transistor performance; limited work has been done to characterize medium-range (≈ 10μm to 2mm) pattern density effects. We propose a new methodology to extract the radius of influence, or the range of neighboring layout that should be taken into account in determining transistor characteristics, for shallow trench isolation (STI) and polysilicon pattern density. A test chip, with 130k devices under test (DUTs) and step-like pattern density layout changes, is designed in 65nm bulk CMOS technology as a case study. The extraction result of the measured data suggests that the local layout geometry, within the DUT cell size of 6μm × 8μm, is the dominant contributor to systematic device variation. Across-die medium-range layout pattern densities are found to have a statistically significant and detectable effect, but this effect is small and contributes only 2-5% of the total variation in this technology.
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science; Massachusetts Institute of Technology. Microsystems Technology Laboratories
Proceedings of the Thirteenth International Symposium on Quality Electronic Design (ISQED)
Institute of Electrical and Electronics Engineers (IEEE)
Chang, Albert H., Kewei Zuo, Jean Wang, Douglas Yu, and Duane Boning. “Test Structure, Circuits and Extraction Methods to Determine the Radius of Infuence of STI and Polysilicon Pattern Density.” Thirteenth International Symposium on Quality Electronic Design (ISQED) (March 2012).
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