Coverage-directed validation of hardware models

Abstract

With the rapid increase in the number of transistors that can be fabricated on a single chip, digital systems have become very complex. The increase in the complexity of the digital systems, and the desire to achieve faster time-to-market has made the use of the Computer-Aided Design (CAD) tools indispensable. Designers typically start with writing behavioral or Register-Transfer level (RTL) description of the system functionality using a Hardware Description Language (HDL). After that they transform the HDL description to the gate-level, transistor level, and finally generate mask-level layout which is used to manufacture the chip. CAD tools are used extensively to execute transformations between different levels of abstraction. They also help to optimize the design so as to achieve better performance and meet different constraints relating to speed, power consumption, and area. In order to have a working chip, the designer has to make sure that the original HDL description is correct and also that no error is introduced during transformations to the lower levels. Currently validation of the initial HDL description and verifying the design in different levels of abstraction against each other is a major bottleneck in the design process. Because the HDL description is usually the first description of the design, simulation is the primary methodology for validating it. Simulation-based verification is necessarily incomplete because it is not computationally feasible to exhaustively simulate designs. It is important therefore to quantitatively measure the degree of verification coverage of the design. Simulation-based validation has suffered from a disconnect between the metrics used to measure the coverage of a set of simulation vectors and the vector generation process. This disconnect has resulted in the simulation of virtually endless streams of vectors which achieve enhanced coverage only infrequently. Another drawback has been that most coverage metrics proposed have either been too simplistic or too inefficient to compute. This thesis provides the details of an efficient method to compute an Observability-based Code COverage Metric (OCCOM) that can be used while simulating complex HDL designs. It also introduces a new method for generating test vectors under any coverage metric. In this thesis the problem of generating test vectors for both combinational and sequential circuits under OCCOM is discussed. A prototype system which generates test vectors under the OCCOM coverage metric has been built. The system can be used during the design process, as well as during post-design debugging to validate the initial HDL description.