A low power video compression chip for portable applications

Abstract

This thesis describes the development of a low power, single chip video encoder intended for battery operated portable applications. Such an encoder is intended to serve as part of the DSP in a portable device which might image, data convert, compress, and transmit video signals. The encoder described in this thesis is designed with the goal of minimizing system power, minimizing utilized bandwidth, and maximizing system integration. The encoder achieves a peak power dissipation of several hundred [mu]W while scalably compressing a video stream of 8 bit gray scale, 30 frame/sec, and 128 x128 demonstration reso lution. The encoder scales up for greater resolutions at mostly linear cost. The compression is performed using wavelet filtering and a combination of zero-tree and arithmetic coding of filter coefficients, all integrated on a single demonstration chip. The compression results achieved (a tradeoff curve of compression factor versus PSNR) are on par with the best available based on wavelet filters. The above results do not include the use of motion compensation, however, hooks are implemented at the algorithmic and architectural levels to add motion compensation at the cost of power dissipation a few times higher. These results are obtained by the careful coordination of design in a deep vertical manner, ranging from system, algorithmic, and architectural to circuit, floor planning, and layout. This thesis describes the motivation of the design goals, the interlinking vertical design choices, and the results achieved.