A real-time 256 x 256 pixel parallel image processing system by Zubair Aman Talib.

Abstract

This thesis explores how a Pixel-Parallel Image Processor (PPIP) chip serves as the basis for a real-time low-level image processing system as used in a machine vision based intelligent vehicle control application. Utilizing a processor-per-pixel scheme, the PPIP integrates 64 x 64 Processing Elements (PEs) on a single chip. Multiple chips can be arrayed to process larger pixel images. Previous work had been done to test and demonstrate the PPIP chip. A data-path and controller board are used in conjunction with a 2 x 2 array (four-chip) PPIP test board to process 128 x 128 pixel images. A revision of the PPIP chip has been tested and characterized. A compact printed-circuit board design utilizes a 4 x 4 array of 16 PPIP chips to process a 256 x 256 pixel image. Logic was designed to govern data transfer to and from the chips and tv govern communication with the existing data-path and controller hardware. Small in size and requiring no test equipment, the PE Array board is suitable for demonstrating an intelligent vehicle control system. While supporting the existing test and demonstration system, the PE Array board is flexible enough to be incorporated into future systems. Although legacy communication protocols limit the data-path to one input image, future designs, for example, will be able to utilize multiple input images.