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dc.contributor.advisorDavid D. Clark.en_US
dc.contributor.authorCharny, Annaen_US
dc.date.accessioned2005-08-19T19:02:52Z
dc.date.available2005-08-19T19:02:52Z
dc.date.copyright1998en_US
dc.date.issued1998en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/9628
dc.descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.en_US
dc.descriptionIncludes bibliographical references (p. 103-105).en_US
dc.description.abstractThis dissertation investigates a number of issues related to providing Quality of Service guarantees in input-buffered crossbar switches with speedup. It is shown that speedup of 4 is sufficient to ensure 100% asymptotic throughput with any maximal matching algorithm employed by the arbiter. It is also demonstrated that the crossbar architecture is capable of providing delay guarantees comparable to those known for output-buffered switch architecture. Several algorithms which ensure different delay guarantees with different values of speedup are presented and analyzed.en_US
dc.description.statementofresponsibilityby Anna Charny.en_US
dc.format.extent105 p.en_US
dc.format.extent7961420 bytes
dc.format.extent7961179 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Scienceen_US
dc.titleProviding QoS guarantees in input buffered crossbar switches with speedupen_US
dc.title.alternativeProviding quality of service guarantees in input buffered crossbar switches with speedupen_US
dc.typeThesisen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Scienceen_US
dc.identifier.oclc42333481en_US


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