Modeling of chemical mechanical polishing for dielectric planarization
Author(s)Ouma, Dennis Okumu
Duane S. Boning and James E. Chung.
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Chemical mechanical polishing (CMP) has emerged as the dielectric planarization method of choice since it can reduce topography over longer length scales than traditional techniques. However, CMP still suffers from large die-level layout pattern dependencies and process induced wafer-level variations. An effective characterization and modeling methodology is needed to facilitate the assessment and reduction of such variation. This thesis identifies the process, consumable, and layout pattern dependencies in inter-level dielectric (ILD) and shallow trench isolation (STI) CMP, and develops a comprehensive semi-physically-based process model and characterization methodology. In the characterization phase, the planarization length of the process is determined. The planarization length is the characteristic length of an elliptic weighting function which captures the long range pad deformation during CMP; it determines the lengthscale over which surrounding features affect the local pressure at a spatial location. Given the planarization length for a process, the effective pattern density across a die can be calculated for any layout. In the modeling phase, a pattern density dependent analytic model is used to predict the temporal film thickness evolution. Polish characteristics of different dies on the wafer are captured through a die-position dependent blanket rate which accounts for blanket rate variation across a wafer. The correct and efficient determination of the planarization length is achieved by using a test layout mask that has step density structures to provide. large abrupt post-CMP thickness variations. Fast Fourier Transform (FFt) is used to compute the effective pattern density during both the characterization and modeling phases. Realistic simulation of film thickness evolution across any die on the wafer is thus possible. Accurate film thickness prediction in CMP is useful for many applications, including process improvement and optimization. Using the model developed in this work, the optimal film thickness that must be deposited for any given planarization requirement can be determined. This results in significant reduction in polish time and slurry waste. In addition to the process related applications, the model is instrumental in assessing the impact of inter-layer dielectric (ILD) thickness variation on circuit performance. Significant reduction of such variation is achieved through a more equitable effective pattern density distribution across a die either by introducing dummy structures, or by using process conditions and consumable sets which result in longer planarization lengths. In either case, the methodology presented in this work simplifies the evaluation of the scheme employed.
Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 1999.Includes bibliographical references (p. 223-238).
DepartmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science