An arbitration state controller for a Digital Equipment Corporation computer bus

Abstract

This thesis will outline the work performed in designing an Arbitration State Controller for a bus conforming to the specifications of Digital Equipment Corporation (DEC) as noted briefly below and as further noted in a DEC specification document. The bus is used to join a processor to integral I/0 controllers, I/0 bus adapters, memories, or other processors. Its characteristics are low cost, short length, high bandwidth, a moderate number of drops, a large addressing range, and data integrity. Arbitration logic is distributed among all devices capable of becoming bus masters (i.e., senders of command/address information). Bus arbitration occurs over a single bus cycle. A device arbitrates for the bus by asserting one of the data lines during an arbi­tration cycle. During the second half of the cycle, the device determines if there were any lower number data lines asserted during the arbitration cycle and if not, then that device wins the bus and may send command/address information when the current bus transaction (if one exists) has completed. Arbitration cycles occur during idle bus cycles or during an imbedded arbitration cycle in a bus transaction and are indicated by the use of the NO ARB signal. The data lines are reserved for arbitration information on the cycle following one which has NO ARB unasserted. An initial design utilizing an encoder, a comparator, a decoder, and random logic has been designed and must be further tested.